1. Field of the Invention
The present invention relates to semiconductor memories, and, more particularly, to a high speed row select circuit and method.
2. Description Of the Prior Art
A row select circuit is used in memory arrays. An array with (2.sup.N) rows requires an address input of (N) bits to select a row. The row select circuit typically includes a decoder circuit and a driver circuit for each row in the array. Each decoder receives and deciphers the (N) bit address input, and in response thereto, one row in the array is selected. The driver circuit of the selected row drives the selected row, thus allowing a memory cell or cells on the selected row to be accessed (read or written into). All of the other rows in the array are deselected. For certain applications such as cache memory on a microprocessor chip, fast access times are desired.
A prior art row select circuit is described in the article entitled "A 1.5-ns Access Time, 78-um2 Memory-Cell Size, 64-kb ECL-CMOS SRAM", IEEE Journal of Solid State Circuits, Vol. 27, No. 2, February, 1992, by Yamaguchi et al. This article teaches a row select circuit (FIG. 3B) using a common emitter coupled logic (ECL) NOR gate configuration. On the first side of the ECL differential configuration, two transistors (Q1 and Q2) are arranged in a NOR gate arrangement. The collectors of the NOR gate transistors are coupled together at a node (hereafter referred to as the "switching node"). The switching node is coupled to a power rail through a pull up resistor. The switching node is used to drive the ECL word line driver transistor Qw. On the second side of the ECL differential configuration, a third transistor is provided with its gate coupled to a reference voltage VBB. The transistors of the differential configuration share a current source coupled to the emitters of the three transistors.
Prior to being selected, Q1 and Q2 are turned on, and the switching node is pulled down. During row select operation, the address signals applied to Q 1 and Q2 both go true (low), and as a result, the transistors turn off. The switching node is pulled up though the resistor, Qw is turned on, and the row is selected.
This aforementioned row select circuit has several disadvantages. The multiple transistors of the NOR decoder create a large amount of capacitance at the switching node. When the NOR gate transistors are turned off, indicating the selection of the row, the capacitance at the switching node slows down the rate at which the node can be pulled up. As a result, access of the row is delayed. Another disadvantage is that the circuit consumes a large amount of power. Each row in the memory array includes a dedicated current source. The current source dissipates power regardless of whether the row is selected or not, and therefore, limits the size of the memory array for a given power budget.
A prior art row driver circuit is described in the Article entitled "An Experimental Soft-Error Immune 64-Kb 3ns Bipolar Ram", Kunihiko Yamaguchi et al., IEEE Bipolar Circuits and Technology Meeting, 1988. This article teaches a two stage Darlington driver circuit (FIG. 2). In response to a row select signal, the two cascaded transistors amplify the current of the row select signal and pull up the selected row. A first discharge circuit is coupled at an intermediate node between the two cascaded transistors. A second discharge circuit is coupled to the output of the second stage of the Darlington (the node which drives the row). A resistor is coupled between the first discharge circuit and the second discharge circuit.
The aforementioned driver circuit has several disadvantages. The two discharge circuits each include a constant current source. These two current sources dissipate power, regardless of whether the row is selected or deselected. Accordingly, the size of a memory array is limited for a given power budget. Although not stated in the Article, it is believed the purpose of the resistor is to shunt current from the intermediate node to the second discharge path. This reduces the over-shoot (bounce) of the Darlington configuration. The resistor, however, impairs the speed performance of the driver circuit because it is always shunting current, even when no overshoot condition is present in the driver circuit. Another disadvantage of the circuit is that the gain of the Darlington is process dependent, i.e., the gain of the transistors are subject to process variations.